1. Field of the Invention
The invention relates in general to a frequency dividing circuit, and more particularly to a frequency dividing circuit for frequency-dividing one set of clock signals with a uniform phase delay into another set of clock signals with a uniform phase delay.
2. Description of the Related Art
In the present circuit applications, some applications sometimes need multiple input clock signals and frequency-divided clock signals thereof to perform the circuit control. In the prior art, multiple flip-flops sample multiple reference signals in response to the rising edge or the falling edge of the input clock signal to generate the frequency-divided clock signals corresponding with the input clock signals, wherein the phase delay between any two neighboring clock signals of the clock signals is equal to a constant, for example. The phase delay between any two neighboring clock signals of the frequency-divided clock signals is also equal to a constant, for example.
However, the prior art cannot perform the effective control on the initial level of each reference signal. Consequently, the frequency-divided clock signal, obtained after the flip-flop samples the input clock signal, may have phase errors. Thus, it is an important subject in the industry to design a frequency dividing circuit capable of effectively preventing the clock signal, obtained after frequency dividing, from having a phase error.